Mastering VHDL & Verilog: Writing Clean Combinational and Sequential Logic

Using VHDL Process or Verilog Always Blocks

In both VHDL and Verilog, Process blocks (VHDL) and Always blocks (Verilog) are the core constructs for describing hardware behavior. They are used to model two distinct types of logic:

1. Combinational logic – outputs depend only on current inputs.
2. Sequential logic – outputs depend on current inputs and past states, typically driven by a clock.

While many textbooks illustrate simple combinational examples, real‑world designs rely almost exclusively on sequential blocks to implement registers, state machines, and pipeline stages.

Why D Flip‑Flops Matter

At the heart of every sequential circuit lies the D flip‑flop, the minimal element that captures and stores a single bit of data on a clock edge. Understanding its timing and setup/hold constraints is essential before diving into higher‑level HDL code.

Readers unfamiliar with D flip‑flop fundamentals should pause here to review basic flip‑flop operation.

Combinational Logic in a Process/Always Block

Although possible, using a Process or Always block solely for combinational assignments is rarely recommended. A direct continuous assignment is clearer and less error‑prone.

VHDL Example

process (input_1, input_2)
begin
    and_gate <= input_1 and input_2;
end process;

Verilog Example

always @ (input_1 or input_2)
  begin
    and_gate = input_1 & input_2;
  end

The sensitivity list (e.g., input_1, input_2) ensures the block executes whenever any listed signal changes. However, the same functionality can be expressed more concisely with a continuous assignment:

-- VHDL
and_gate <= input_1 and input_2;

// Verilog
assign and_gate = input_1 & input_2;

These statements are equivalent in effect but the continuous assignment is preferred for pure combinational logic.

Sequential Logic: The Common Use Case

Process (VHDL) and Always (Verilog) blocks shine when modeling clock‑driven behavior. A typical pattern includes a sensitivity list that includes the clock and optional asynchronous reset:

VHDL Sequential Example

process (clk, rst_n)
begin
    if rst_n = '0' then
        q <= '0';
    elsif rising_edge(clk) then
        q <= d;
    end if;
end process;

Verilog Sequential Example

always @(posedge clk or negedge rst_n)
begin
    if (!rst_n)
        q <= 1'b0;
    else
        q <= d;
end

These snippets illustrate how a D flip‑flop is instantiated implicitly by the HDL. Designers should employ this pattern whenever a signal must be registered or state must be maintained.

Best Practices

• Use continuous assignments for pure combinational logic.
• Reserve Process/Always blocks for sequential logic that requires clock edges or asynchronous control.
• Always include clear reset handling to avoid inferred latches.
• Keep sensitivity lists explicit and minimal to prevent simulation mismatches.

By following these guidelines, you’ll write HDL that is both efficient to synthesize and straightforward to verify.