Half‑Adder: Building a Basic Binary Addition Circuit
In digital electronics, the half‑adder is the simplest combinational circuit that adds two single‑bit binary numbers. It produces two outputs: the low‑order sum (Σ) and the high‑order carry out (C_{out}). Understanding this device is foundational for designing more complex arithmetic units such as full adders and binary adders used in CPUs, DSPs, and digital signal processors.
Below is the truth table that summarizes the expected outputs for every possible input pair:
| A | B | Σ | C_{out} |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
The logical relationships revealed by the table are straightforward: the sum output is the exclusive‑OR (XOR) of the two inputs, while the carry‑out is simply the logical AND of the inputs. A minimal implementation of these logic functions yields the classic half‑adder schematic shown below.
For those who prefer ladder logic, the equivalent representation is also provided:
While a half‑adder can only add two single bits, it serves as a critical building block for constructing full adders, which incorporate a carry‑in input. Full adders are combined in cascaded arrays to create ripple‑carry adders, carry‑lookahead adders, and other advanced arithmetic logic units.
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