View the RTOS Revealed series This article continues the look at semaphores. Semaphore Utility Services Nucleus RTOS offers four API calls that provide essential utilities for semaphore management: reset a semaphore, retrieve detailed semaphore information, count the total number of semaphores in

View the RTOS Revealed series Mailboxes were introduced in an earlier article as one of the most straightforward inter‑task communication mechanisms in Nucleus SE—right after signals. They offer a low‑cost, highly flexible way to transfer simple data between tasks. Using Mailboxes In Nucleus SE, ma

Since its debut in 2011, the ARMv8 architecture has become ubiquitous in mobile devices. Forecasts from ARM Limited’s CEO projected that ARMv8 processors would capture up to 25 % of the global market by 2020. Naturally, software support has followed suit, evolving by inheriting the features and prin

Editor's note: Max is actively seeking suggestions for electronic calculators and solvers to enhance EEWeb’s toolkit. Let us know which tools you believe deserve a spot on our curated list. Occasionally, a bright spark of inspiration lights up the day—today’s revelation is no exception. I was ju

As someone who has both launched and supported a range of crowdfunding projects, I frequently receive inquiries from creators looking to streamline their prototypes. One such message came from Forrest Bao, who announced an open‑source project that promises to eliminate the need for jumper wires betw

As high-speed analog-to-digital converters (ADCs) have increased in sampling rate, so has the problem of code errors — also known as sparkle codes — in the ADC’s output data. A code error is defined as an error in the output code of an ADC that exceeds a defined threshold. The threshold is

In my previous article, “Arm Cortex‑M low‑power mode fundamentals,” I outlined the basic low‑power states available on every Cortex‑M processor and how to use the WFI and WFE instructions to enter sleep. The next logical question is: how are these modes implemented on real microcontrollers, and wha

Power is the single largest cost driver in semiconductor design. A chip that consumes more energy requires larger, more expensive batteries for portable devices, higher‑grade cooling solutions, and more robust power‑distribution systems. These additional components drive up manufacturing costs, shri

Today’s electronics demand compact, low‑power packages that integrate signal processing, sensors, imaging, and power management—all within increasingly tighter dimensions and sometimes on flexible substrates. These requirements challenge traditional rigid PCBs, pushing designers toward new miniaturi

Since the dawn of electronics design, bugs have been inevitable, and debugging has been the essential discipline to wrestle faults and errors to determine which will prevail—and how thoroughly. Debugging technology has evolved as fascinatingly as the designs it supports. From simple stimulus–respons

In modern VLSI designs, a reliable reset mechanism is essential for establishing a known start‑up state. This article examines the coordination challenges between asynchronous resets and synchronous clocks, and presents proven strategies for both ASIC and FPGA environments. Asynchronous resets are w

Introduction Asynchronous resets are the first line of defense in VLSI circuits, ensuring that all synchronous logic starts from a known state after power‑up. When the release of the reset signal is not carefully coordinated with the clock domains, designers can encounter intermittent, hard‑to‑track

There is a vast array of Real‑Time Operating Systems (RTOS) available online (see a curated list here). Unfortunately, many of those projects are now abandoned or no longer maintained. Of the few that remain active, most target a single microcontroller or a narrow family of chips. Even the multi‑pla

Recently, Brian Bailey convened a round‑table that culminated in the two‑part article Supporting CPUs + FPGAs. Experts debated the evolving reality of systems that fuse FPGAs with CPUs, spotlighting how fresh design flows empower software developers to bring CPU‐plus‐FPGA platforms to market faster.

For more than a decade, I’ve followed Achronix’s evolution—from pioneering asynchronous FPGA fabrics to today’s cutting‑edge embedded solutions that deliver performance rivaling a 2‑GHz synchronous device, yet with a far broader range of applications. In 2013 Achronix launched the Speedster family o

Hearables and truly wireless stereo earbuds are rapidly gaining traction, yet their full potential remains largely untapped. These compact devices promise to redefine how we interact with our surroundings—offering heightened hearing, richer enjoyment, and increased safety in everyday life. While the

Editors Note: Wireless PCB design can derail even the best plans if the RF feedline isn’t engineered correctly. This article, adapted from EEWeb, details how Arira Design’s Signal Integrity Group tackled a 5 GHz grounded coplanar waveguide (GCPW) that was under‑impedance and causing Wi‑Fi degradatio

In recent years, breakthroughs in automatic speech recognition (ASR) have turned voice from a novelty into a primary interface for countless devices. IEEE Spectrum dubbed 2017 the “year of voice recognition,” and ZDNet reported at CES that voice is the next major computer interface. Here’s an overvi

Throughout my career, I have designed numerous FPGA solutions for a broad spectrum of applications. Unfortunately, I have also had to rescue several projects that had gone off course. While each case involved distinct applications and teams, a recurring pattern emerged: these designs shared common t

5G – the fifth generation of mobile networks – is rapidly moving from concept to reality. While initial deployments began in 2020, the standards are still evolving, and many specifications remain in flux. But what exactly does 5G promise? The NGMN Alliance outlines several key performance indicators